Configurable buffer circuits and methods

ABSTRACT

A buffer circuit includes first and second inputs and first and second outputs. The buffer circuit is configurable to buffer a differential input signal received at the first and the second inputs to generate a differential output signal at the first and the second outputs in a current mode logic buffer mode based on a control signal. The buffer circuit is configurable to buffer the differential input signal to generate the differential output signal in an H-bridge buffer mode based on the control signal.

CROSS REFERENCE TO RELATED APPLICATION

This patent application is a continuation of U.S. patent applicationSer. No. 12/910,177, filed Oct. 22, 2010 now U.S. Pat. No. 8,174,294,which is incorporated by reference herein in its entirety.

FIELD OF THE DISCLOSURE

The present invention relates to electronic circuits, and moreparticularly, to configurable buffer circuits and methods.

BACKGROUND

FIG. 1 illustrates a prior art current mode logic (CML) buffer circuit100 that is used in a transmitter circuit. CML buffer circuit 100includes constant current source circuit 101, switch circuits 102-103,and resistors 104-105. CML buffer circuit 100 is coupled between a nodeat a supply voltage VCC and a node at a low voltage VSS (e.g., ground).

CML buffer circuit 100 buffers a differential input signal VIN togenerate a differential output signal VOUT. The differential inputsignal VIN is based on input voltage signals IN and INB (i.e.,VIN=IN−INB). The differential output signal VOUT is based on outputvoltage signals VOP and VON (i.e., VOUT=VOP−VON). The conductive statesof switch circuits 102-103 are controlled by input voltage signals INand INB, respectively. Input voltage signal INB is the logical inverseof input voltage signal IN. The voltage range for both of signals IN andINB is from voltage VSS to voltage VH, where VH is the voltage of thenode between switch circuits 102 and 103. CML buffer circuit 100generates output voltage signal VOP between switch circuit 102 andresistor 104. CML buffer circuit 100 generates output voltage signal VONbetween switch circuit 103 and resistor 105.

When input voltage signal IN is in a logic high state, switch circuit102 is closed, input voltage signal INB is in a logic low state causingswitch circuit 103 to be open, and the current I1 from current sourcecircuit 101 flows through switch circuit 102. Differential output signalVOUT equals I1×R1, where R1 equals the resistance of each of resistors104-105.

When input voltage signal IN is in a logic low state, switch circuit 102is open, input voltage signal INB is in a logic high state causingswitch circuit 103 to be closed, and the current I1 from current sourcecircuit 101 flows through switch circuit 103. Differential output signalVOUT equals −I1×R1.

The common mode voltage VCM of CML buffer circuit 100 equals (I1×R1)/2.The peak-to-peak differential voltage swing of the differential outputsignal VOUT equals 2×I1×R1.

FIG. 2 illustrates a prior art H-bridge buffer circuit 200 that is usedin a transmitter circuit. H-bridge buffer circuit 200 includes constantcurrent sources 201-202, switch circuits 203-206, and resistors 207-208.H-bridge buffer circuit 200 is coupled between a node at a supplyvoltage VCC and a node at a low voltage VSS.

H-bridge buffer circuit 200 buffers a differential input signal VIN togenerate a differential output signal VOUT. The differential inputsignal VIN is based on input voltage signals IN and INB (i.e.,VIN=IN−INB). The differential output signal VOUT is based on outputvoltage signals VOP and VON (i.e., VOUT=VOP−VON). The conductive statesof switch circuits 203 and 206 are controlled by input voltage signalIN, and the conductive states of switch circuits 204-205 are controlledby input voltage signal INB. Input voltage signal INB is the logicinverse of input voltage signal IN. H-bridge buffer circuit 200generates output voltage signal VOP between switch circuits 203-204.H-bridge buffer circuit 200 generates output voltage signal VON betweenswitch circuits 205-206.

H-bridge buffer circuit 200 also includes a circuit such as an amplifier(not shown) that generates a constant voltage VCM between resistors207-208. Voltage VCM equals the common mode voltage of output voltagesignals VOP and VON.

When input voltage signal IN is in a logic high state, switch circuits203 and 206 are closed, input voltage signal INB is in a logic low statecausing switch circuits 204-205 to be open, and the current I2 fromcurrent source 201 flows through switch circuit 203, resistors 207-208,switch circuit 206, and current source 202. Differential output signalVOUT equals I2×2×R2, where R2 equals the resistance of each of resistors207-208.

When input voltage signal IN is in a logic low state, switch circuits203 and 206 are open, input voltage signal INB is in a logic high statecausing switch circuits 204-205 to be closed, and the current I2 fromcurrent source 201 flows through switch circuit 205, resistors 208 and207, switch circuit 204, and current source 202. Differential outputsignal VOUT equals −I2×2×R2.

H-bridge buffer circuit 200 generates a peak-to-peak differentialvoltage swing in VOUT that equals 4×I2×R2. If R1 equals R2, thenH-bridge buffer circuit 200 draws half as much current as CML buffercircuit 100 to achieve the same output voltage swing in VOUT (i.e.,I1=2×I2). As a result, H-bridge buffer circuit 200 consumes less powerthan CML buffer circuit 100.

However, H-bridge buffer circuit 200 generates a more limited range inthe common mode voltage VCM of the differential output signal VOUT thanCML buffer circuit 100. The common mode voltage VCM of the differentialoutput signal VOUT of H-bridge buffer circuit 200 is limited based onthe equation VCM≧(I2×R2)+VL+VSW2, where VL is the voltage of the nodebetween switch circuits 204 and 206, and VSW2 is the voltage drop acrossswitch circuit 204 or 206.

H-bridge buffer circuit 200 has less voltage headroom between supplyvoltage VCC and low voltage VSS compared to CML buffer circuit 100,because H-bridge buffer circuit 200 includes two current source circuits201-202 that each consume a portion of the voltage drop between VCC andVSS. In addition, H-bridge buffer circuit 200 has a higher outputcapacitance than CML buffer circuit 100 at the nodes that generateoutput voltage signals VOP and VON. The higher output capacitance inH-bridge buffer circuit 200 slows down transitions in output voltagesignals VOP and VON. H-bridge buffer circuit 200 generates moresymmetrical waveforms in output voltage signals VOP and VON than CMLbuffer circuit 100.

BRIEF SUMMARY

According to some embodiments, a buffer circuit includes first andsecond inputs and first and second outputs. The buffer circuit isconfigurable to buffer a differential input signal received at the firstand the second inputs to generate a differential output signal at thefirst and the second outputs in a current mode logic buffer mode basedon a control signal. The buffer circuit is configurable to buffer thedifferential input signal to generate the differential output signal inan H-bridge buffer mode based on the control signal.

Various objects, features, and advantages of the present invention willbecome apparent upon consideration of the following detailed descriptionand the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a prior art current mode logic (CML) buffer circuitthat is used in a transmitter circuit.

FIG. 2 illustrates a prior art H-bridge buffer circuit that is used in atransmitter circuit.

FIG. 3A illustrates an example of a DC coupled transmission system thatcan include embodiments of the present invention.

FIG. 3B illustrates an example of an AC coupled transmission system thatcan include embodiments of the present invention.

FIG. 4 illustrates an example of a configurable buffer circuit,according to an embodiment of the present invention.

FIGS. 5A-5B illustrate examples of logic circuits that generate controlsignals shown in FIG. 4, according to embodiments of the presentinvention.

FIG. 5C illustrates an example of an amplifier circuit that generatesthe common mode voltage VCM of differential output voltage signal VOUTat its output.

FIG. 6 illustrates the configurable buffer circuit of FIG. 4 when it isconfigured as a pseudo-CML buffer circuit in CML buffer mode.

FIG. 7 is a simplified partial block diagram of a field programmablegate array (FPGA) that can include aspects of the present invention.

FIG. 8 shows a block diagram of an exemplary digital system that canembody techniques of the present invention.

DETAILED DESCRIPTION

FIG. 3A illustrates an example of a direct current (DC) coupledtransmission system. The transmission system of FIG. 3A includes twointegrated circuits 301-302. Integrated circuit 301 includes atransmitter circuit 303. Integrated circuit 302 includes a receivercircuit 304. Transmitter circuit 303 generates output voltage signalsVOP and VON based on input signals IN and INB. Output signals VOP andVON are transmitted from outputs of transmitter circuit 303 throughtransmission lines 305-306, respectively, to inputs of receiver circuit304. Transmitter circuit 303 and receiver circuit 304 are DC coupledthrough transmission lines 305-306. Receiver circuit 304 generatesoutput signals OUT and OUTB based on signals VOP and VON.

FIG. 3B illustrates an example of an alternating current (AC) coupledtransmission system. The transmission system of FIG. 3B includesintegrated circuits 311-312. Integrated circuit 311 includes transmittercircuit 313. Integrated circuit 312 includes receiver circuit 314.Transmitter circuit 313 generates output voltage signals VOP and VONbased on input signals IN and INB. Output signals VOP and VON aretransmitted from outputs of transmitter circuit 313 to inputs ofreceiver circuit 314 through transmission lines. The transmission linesare coupled to capacitors 315-316. The outputs of transmitter circuit313 are AC coupled to the inputs of receiver circuit 314 throughcapacitors 315-316. Receiver circuit 314 generates output signals OUTand OUTB based on signals VOP and VON.

FIG. 4 illustrates an example of a configurable buffer circuit 400,according to an embodiment of the present invention. Configurable buffercircuit 400 can be used in a transmitter circuit. As an example,configurable buffer circuit 400 can be used in transmitter circuit 303in the DC coupled transmission system of FIG. 3A. As another example,configurable buffer circuit 400 can be used in transmitter circuit 313in the AC coupled transmission system of FIG. 3B. Configurable buffercircuit 400 is coupled between a node at a supply voltage VCC and a nodeat a ground voltage VSS. As an example that is not intended to belimiting, supply voltage VCC may have a fixed voltage that is in a rangebetween 1.2-1.5 volts and ground voltage VSS may be at 0 volts.

Configurable buffer circuit 400 buffers a differential input voltagesignal VIN to generate a differential output voltage signal VOUT. Thedifferential input voltage signal VIN is based on two digital inputvoltage signals IN and INB. Input voltage signal INB is driven to equalthe logical inverse of input voltage signal IN by an inverter (notshown). The voltage swing of IN and INB is limited between the groundvoltage VSS and voltage VH, where voltage VH is the voltage of the nodebetween switch circuits 404 and 406. The differential input voltagesignal VIN=IN−INB. The differential output voltage signal VOUT is basedon two output voltage signals VOP and VON. The differential outputvoltage signal VOUT=VOP−VON.

Configurable buffer circuit 400 includes current source circuits401-403, switch circuits 404-407 and 410-411, and resistors 408-409.Configurable buffer circuit 400 generates output voltage signal VOPbetween switch circuits 404-405. Configurable buffer circuit 400generates output voltage signal VON between switch circuits 406-407. Theconductive states of switch circuits 404 and 406 are controlled bydigital input voltage signals IN and INB, respectively. The conductivestates of switch circuits 405, 407, 410, and 411 are controlled bycontrol signals S1, S2, S3, and S4, respectively. Each of switchcircuits 404-407 and 411 can be implemented, for example, by one ormultiple field-effect transistors (FETs). Switch circuit 410 can beimplemented, for example, by multiple FETs. The currents generated bycurrent source circuits 401-403 can be programmable.

FIGS. 5A-5B illustrate examples of logic circuits that generate controlsignals S1-S2, respectively, according to embodiments of the presentinvention. FIG. 5A shows an AND logic gate circuit 501. AND logic gatecircuit 501 receives input voltage signal INB at a first input and adigital MODE signal at a second input. AND logic gate circuit 501performs an AND Boolean logic function on signals INB and MODE togenerate the logic state of control signal S1. FIG. 5B shows an ANDlogic gate circuit 502. AND logic gate circuit 502 receives inputvoltage signal IN at a first input and the MODE signal at a secondinput. AND logic gate circuit 502 performs an AND Boolean logic functionon signals IN and MODE to generate control signal S2. According to otherembodiments, AND logic gate circuits 501-502 are replaced with othertypes of logic gate circuits that generate signals S1-S2.

Referring again to FIG. 4, configurable buffer circuit 400 isconfigurable to operate either in an H-bridge buffer mode or in acurrent mode logic (CML) buffer mode. The MODE signal controls whetherconfigurable buffer circuit 400 is configured to operate in the H-bridgebuffer mode or in the CML buffer mode.

The MODE signal is driven to a logic high state to cause configurablebuffer circuit 400 to function as an H-bridge buffer circuit in theH-bridge buffer mode. When the MODE signal is in a logic high state, ANDgate circuits 501 and 502 cause control signals S1 and S2 to have thesame logic states as input voltage signals INB and IN, respectively. InH-bridge buffer mode, switch circuit 405 has the same conductive stateas switch circuit 406, and switch circuit 407 has the same conductivestate as switch circuit 404.

When the MODE signal is in a logic high state, control signal S4 isdriven to a logic state that causes switch circuit 411 to be open. Whenswitch circuit 411 is open, current source circuit 402 is decoupled fromthe node at supply voltage VCC, and no current flows from current sourcecircuit 402 through configurable buffer circuit 400. Also, when the MODEsignal is in a logic high state, control signal S3 is driven to a logicstate that causes switch circuit 410 to couple resistors 408-409 to anode at a common mode voltage VCM of the differential output voltagesignal VOUT and to decouple resistors 408-409 from a node at VSS. Switchcircuit 410 can, for example, be implemented by a first FET coupledbetween resistors 408-409 and the node at VCM, and a second FET coupledbetween resistors 408-409 and the node at VSS.

FIG. 5C illustrates an example of an amplifier circuit 503 thatgenerates the common mode voltage VCM of differential output voltagesignal VOUT at its output. Amplifier circuit 503 receives a referencevoltage VREF at its non-inverting input. Reference voltage VREF equalsan expected common mode voltage of differential output voltage signalVOUT. The output of amplifier circuit 503 is coupled to the invertinginput of amplifier circuit 503. Amplifier circuit 503 drives the voltagedifference between VREF and VCM to zero or near zero. Amplifier circuit503 can, for example, include a source-follower transistor.

When input voltage signal IN is in a logic high state in H-bridge buffermode, switch circuits 404 and 407 are closed, input voltage signal INBis in a logic low state causing switch circuits 405-406 to be open, andthe current I3 from current source 401 flows through switch circuit 404,resistors 408-409, switch circuit 407, and current source circuit 403 toVSS. When input voltage signal IN is in the logic high state,differential output signal VOUT equals I3×2×R3, where R3 equals theresistance of each of resistors 408-409.

When input voltage signal IN is in a logic low state in H-bridge buffermode, switch circuits 404 and 407 are open, input voltage signal INB isin a logic high state causing switch circuits 405-406 to be closed, andthe current I3 from current source 401 flows through switch circuit 406,resistors 409 and 408, switch circuit 405, and current source circuit403 to VSS. When input voltage signal IN is in a logic low state,differential output signal VOUT equals −I3×2×R3.

The MODE signal is driven to a logic low state to cause configurablebuffer circuit 400 to function as a pseudo-CML buffer circuit in the CMLbuffer mode. When the MODE signal is in a logic low state, AND gates501-502 drive control signals S1-S2 to logic low states that causeswitch circuits 405 and 407 to be open in the CML buffer mode,respectively, regardless of the logic states of input signals IN andINB.

When the MODE signal is in a logic low state, control signal S4 isdriven to a logic state that causes switch circuit 411 to be closed.When switch circuit 411 is closed, current source circuit 402 is coupledto the node at supply voltage VCC, and a current I3 from current sourcecircuit 402 flows through one of switch circuits 404 or 406. In CMLbuffer mode, each of the 2 current source circuits 401-402 generates thesame current, and the current through each of current source circuits401-402 equals I3. In the CML buffer mode, current source circuit 403 isin a floating state, and no current flows through current source circuit403. Also, when the MODE signal is in a logic low state, control signalS3 is driven to a logic state that causes switch circuit 410 to coupleresistors 408-409 to the node at voltage VSS and to decouple resistors408-409 from the node at voltage VCM.

FIG. 6 illustrates configurable buffer circuit 400 when it is configuredas a pseudo-CML buffer circuit in CML buffer mode. As shown in FIG. 6,switch circuits 410-411 function as resistors in the CML buffer modewhen switch circuit 411 is closed and switch circuit 410 is coupled tothe node at voltage VSS. The field-effect transistors used to implementswitch circuits 410-411 have relatively large width-to-length channelratios so that switch circuits 410-411 have low drain-to-sourceresistances and small voltage drops. The small voltage drop acrossswitch circuit 410 in the CML buffer mode causes node 420 to be at avoltage that is greater than voltage VSS. The resistance of switchcircuit 410 has no impact on the differential output return loss ofconfigurable buffer circuit 400. However, the resistance of switchcircuit 410 may cause a small increase in the common mode output returnloss of configurable buffer circuit 400.

In CML buffer mode, a current equal to 2×I3 flows through configurablebuffer circuit 400 from the node at VCC to the node at VSS. The current2×I3 that flows through configurable buffer circuit 400 in CML buffermode is two times the current I3 that flows through configurable buffercircuit 400 in H-bridge buffer mode. Doubling the current throughconfigurable buffer circuit 400 in CML buffer mode compared to H-bridgebuffer mode causes the output voltage swing VOD of differential outputvoltage signal VOUT to be the same in both the CML buffer mode and inthe H-bridge buffer mode. The peak-to-peak differential voltage swingVOD of the differential output signal VOUT in CML buffer mode equals4×I3×R3, where R3 equals the resistance of each of resistors 408-409.

When input voltage signal IN is in a logic high state in CML buffermode, switch circuit 404 is closed, input voltage signal INB is in alogic low state causing switch circuit 406 to be open, and the current2×I3 generated by current source circuits 401-402 flows through switchcircuit 404, resistor 408, and switch circuit 410 to VSS. Differentialoutput signal VOUT equals 2×I3×R3, where VSS equals zero volts, andVOUT=VOP−VON.

When input voltage signal IN is in a logic low state in CML buffer mode,switch circuit 404 is open, input voltage signal INB is in a logic highstate causing switch circuit 406 to be closed, and the current 2×I3generated by current source circuits 401-402 flows through switchcircuit 406, resistor 409, and switch circuit 410 to VSS. Differentialoutput signal VOUT equals −2×I3×R3, where VSS equals zero volts.

In an embodiment of configurable buffer circuit 400, each of the switchcircuits 404 and 406 is implemented by a single p-channel metal oxidesemiconductor field-effect transistor (MOSFET), and each of the switchcircuits 405 and 407 is implemented by a single n-channel MOSFET. Inthis embodiment, the gate voltages of the p-channel MOSFETs in switchcircuits 404 and 406 are not pulled above voltage VH at node 421 (shownin FIG. 6) to open the respective switch circuit 404 or 406, so that theopened switch circuit 404 or 406 can be closed quickly. However, each ofthe switch circuits 404 and 406 may generate some leakage current whenthe respective switch circuit 404 or 406 is open. This leakage currentmay increase the output return loss of configurable buffer circuit 400.Also, the MOSFET in each of switch circuits 404 and 406 is preferablymaintained in saturation when the respective switch circuit 404 or 406is closed in CML buffer mode.

Configurable buffer circuit 400 is configurable to operate in CML buffermode or in H-bridge buffer mode. Configurable buffer circuit 400 cansupport protocols that require the transmitter circuit to be connectedto the receiver circuit via DC coupled or AC coupled transmission linesas shown in FIGS. 3A-3B. As an example, configurable buffer circuit 400can be configured in CML buffer mode in a transmitter circuit to supportthe QuickPath Interconnect (QPI) protocol. Configurable buffer circuit400 requires substantially less die area and has less output parasiticloading than a transmitter circuit that has an H-bridge buffer circuitand a separate CML buffer circuit that are coupled to the same outputpads, but one of the H-bridge buffer circuit or CML buffer circuit isdisabled.

FIG. 7 is a simplified partial block diagram of a field programmablegate array (FPGA) 700 that can include aspects of the present invention.FPGA 700 is merely one example of an integrated circuit that can includefeatures of the present invention. It should be understood thatembodiments of the present invention can be used in numerous types ofintegrated circuits such as field programmable gate arrays (FPGAs),programmable logic devices (PLDs), complex programmable logic devices(CPLDs), programmable logic arrays (PLAs), application specificintegrated circuits (ASICs), memory integrated circuits, centralprocessing units, microprocessors, analog integrated circuits, etc.

FPGA 700 includes a two-dimensional array of programmable logic arrayblocks (or LABs) 702 that are interconnected by a network of column androw interconnect conductors of varying length and speed. LABs 702include multiple (e.g., 10) logic elements (or LEs).

An LE is a programmable logic circuit block that provides for efficientimplementation of user defined logic functions. An FPGA has numerouslogic elements that can be configured to implement various combinatorialand sequential functions. The logic elements have access to aprogrammable interconnect structure. The programmable interconnectstructure can be programmed to interconnect the logic elements in almostany desired configuration.

FPGA 700 also includes a distributed memory structure including randomaccess memory (RAM) blocks of varying sizes provided throughout thearray. The RAM blocks include, for example, blocks 704, blocks 706, andblock 708. These memory blocks can also include shift registers andfirst-in-first-out (FIFO) buffers.

FPGA 700 further includes digital signal processing (DSP) blocks 710that can implement, for example, multipliers with add or subtractfeatures. Input/output elements (IOEs) 712 located, in this example,around the periphery of the chip, support numerous single-ended anddifferential input/output standards. IOEs 712 include input and outputbuffers that are coupled to pads of the integrated circuit. The outputbuffers may include configurable buffer circuit 400 shown in FIG. 4. Thepads are external terminals of the FPGA die that can be used to route,for example, input signals, output signals, and supply voltages betweenthe FPGA and one or more external devices. It should be understood thatFPGA 700 is described herein for illustrative purposes only and that thepresent invention can be implemented in many different types ofintegrated circuits.

The present invention can also be implemented in a system that has anFPGA as one of several components. FIG. 8 shows a block diagram of anexemplary digital system 800 that can embody techniques of the presentinvention. System 800 can be a programmed digital computer system,digital signal processing system, specialized digital switching network,or other processing system. Moreover, such systems can be designed for awide variety of applications such as telecommunications systems,automotive systems, control systems, consumer electronics, personalcomputers, Internet communications and networking, and others. Further,system 800 can be provided on a single board, on multiple boards, orwithin multiple enclosures.

System 800 includes a processing unit 802, a memory unit 804, and aninput/output (I/O) unit 806 interconnected together by one or morebuses. According to this exemplary embodiment, an FPGA 808 is embeddedin processing unit 802. FPGA 808 can serve many different purposeswithin the system of FIG. 8. FPGA 808 can, for example, be a logicalbuilding block of processing unit 802, supporting its internal andexternal operations. FPGA 808 is programmed to implement the logicalfunctions necessary to carry on its particular role in system operation.FPGA 808 can be specially coupled to memory 804 through connection 810and to I/O unit 806 through connection 812.

Processing unit 802 can direct data to an appropriate system componentfor processing or storage, execute a program stored in memory 804,receive and transmit data via I/O unit 806, or other similar functions.Processing unit 802 can be a central processing unit (CPU),microprocessor, floating point coprocessor, graphics coprocessor,hardware controller, microcontroller, field programmable gate arrayprogrammed for use as a controller, network controller, or any type ofprocessor or controller. Furthermore, in many embodiments, there isoften no need for a CPU.

For example, instead of a CPU, one or more FPGAs 808 can control thelogical operations of the system. As another example, FPGA 808 acts as areconfigurable processor that can be reprogrammed as needed to handle aparticular computing task. Alternatively, FPGA 808 can itself include anembedded microprocessor. Memory unit 804 can be a random access memory(RAM), read only memory (ROM), fixed or flexible disk media, flashmemory, tape, or any other storage means, or any combination of thesestorage means.

The foregoing description of the exemplary embodiments of the presentinvention has been presented for the purposes of illustration anddescription. The foregoing description is not intended to be exhaustiveor to limit the present invention to the examples disclosed herein. Insome instances, features of the present invention can be employedwithout a corresponding use of other features as set forth. Manymodifications, substitutions, and variations are possible in light ofthe above teachings, without departing from the scope of the presentinvention.

1. A buffer circuit comprising: first and second inputs; and first andsecond outputs; wherein the buffer circuit is configurable to buffer adifferential input signal received at the first and the second inputs togenerate a differential output signal at the first and the secondoutputs in a current mode logic buffer mode, and wherein the buffercircuit is configurable to buffer the differential input signal togenerate the differential output signal in an H-bridge buffer mode;first and second resistors; and a first switch circuit coupled to thefirst and the second resistors, wherein the first switch circuit isoperable to couple the first and the second resistors to a node at afirst voltage when the buffer circuit is configured to function in thecurrent mode logic buffer mode, and wherein the first switch circuit isoperable to couple the first and the second resistors to a node at asecond voltage when the buffer circuit is configured to function in theH-bridge buffer mode.
 2. The buffer circuit of claim 1 wherein, acontrol signal controls whether the buffer circuit is configured tooperate in the H-bridge buffer mode or in the current mode logic buffermode.
 3. The buffer circuit of claim 2 further comprising: a firstcurrent source circuit; and second and third switch circuits that arecoupled to the first current source circuit, wherein the first resistoris coupled to the second switch circuit, and wherein the second resistoris coupled to the third switch circuit.
 4. The buffer circuit of claim 3further comprising: a fourth switch circuit coupled to the second switchcircuit; a fifth switch circuit coupled to the fourth and the thirdswitch circuits; and a second current source circuit having a firstterminal coupled to the fourth and the fifth switch circuits and asecond terminal coupled to a node at the first voltage.
 5. The buffercircuit of claim 4 further comprising: a third current source circuitcoupled to the second and the third switch circuits; and a sixth switchcircuit coupled between a node at a supply voltage and the third currentsource circuit, wherein the sixth switch circuit is operable to couplethe third current source circuit to the node at the supply voltage whenthe buffer circuit is configured to function in the current mode logicbuffer mode, and wherein the sixth switch circuit is operable todecouple the third current source circuit from the node at the supplyvoltage when the buffer circuit is configured to function in theH-bridge buffer mode.
 6. The buffer circuit of claim 4, wherein thecontrol signal causes the buffer circuit to maintain the fourth and thefifth switch circuits concurrently open when the buffer circuit isconfigured to function in the current mode logic buffer mode.
 7. Thebuffer circuit of claim 3, wherein the first output is between thesecond switch circuit and the first resistor, and wherein the secondoutput is between the third switch circuit and the second resistor. 8.The buffer circuit of claim 7 further comprising: an amplifier operableto generate the second voltage as a common mode voltage of thedifferential output signal.
 9. A circuit comprising: first and secondinputs; first and second outputs; wherein the circuit is operable tobuffer a differential input signal received at the first and the secondinputs to generate a differential output signal at the first and thesecond outputs, wherein the circuit is configurable to operate in acurrent mode logic buffer mode, and wherein the circuit is configurableto operate in an H-bridge buffer mode; and a first current sourcecircuit coupled to a node at a supply voltage through a first switchcircuit during the current mode logic buffer mode, wherein the firstcurrent source circuit is decoupled from the node at the supply voltageusing the first switch circuit during the H-bridge buffer mode.
 10. Thecircuit of claim 9, wherein a control signal controls whether thecircuit is configured to operate in the H-bridge buffer mode or in thecurrent mode logic buffer mode.
 11. The circuit of claim 10 furthercomprising: a second current source circuit; a second switch circuitcoupled to the second current source circuit; and a third switch circuitcoupled to the second switch circuit.
 12. The circuit of claim 11further comprising: a first resistor coupled to the second switchcircuit; a second resistor coupled to the third switch circuit; and afourth switch circuit coupled to the first and the second resistors,wherein the fourth switch circuit is operable to couple the first andthe second resistors to a node at a second voltage when the circuit isconfigured to function in the current mode logic buffer mode, andwherein the fourth switch circuit is operable to couple the first andthe second resistors to a node at a third voltage when the circuit isconfigured to function in the H-bridge buffer mode.
 13. The circuit ofclaim 12 further comprising: a fifth switch circuit coupled to thesecond switch circuit; a sixth switch circuit coupled to the fifth andthe third switch circuits; and a third current source circuit having afirst terminal coupled to the fifth and the sixth switch circuits and asecond terminal coupled to a node at the second voltage.
 14. The circuitof claim 13, wherein the control signal causes the circuit to open thefifth and the sixth switch circuits when the circuit is configured tofunction in the current mode logic buffer mode.
 15. The circuit of claim11 wherein, the first current source circuit is coupled to the secondand the third switch circuits.
 16. A method comprising: buffering adifferential input signal received at first and second inputs of abuffer circuit to generate a differential output signal at first andsecond outputs of the buffer circuit in a current mode logic buffer modebased on a control signal, wherein a first current source is coupled toa node at a supply voltage through a first switch circuit during thecurrent mode logic buffer mode; and buffering the differential inputsignal received at the first and the second inputs to generate thedifferential output signal at the first and the second outputs in anH-bridge buffer mode based on the control signal, wherein the firstcurrent source is decoupled from the node at the supply voltage throughthe first switch circuit during the H-bridge buffer mode.
 17. The methodof claim 16, wherein buffering the differential input signal received atthe first and the second inputs to generate the differential outputsignal at the first and the second outputs in an H-bridge buffer modebased on the control signal further comprises: providing current from asecond current source through a second switch circuit, a first resistor,a second resistor, a third switch circuit, and a third current sourcebased on a first input signal during the H-bridge buffer mode; andproviding the current from the second current source through a fourthswitch circuit, the first resistor, the second resistor, a fifth switchcircuit, and the third current source based on a second input signalduring the H-bridge buffer mode.
 18. The method of claim 17 wherein, thecontrol signal causes the third and the fifth switch circuits to be openduring the current mode logic is buffer mode.
 19. A method comprising:buffering a differential input signal received at first and secondinputs of a buffer circuit to generate a differential output signal atfirst and second outputs of the buffer circuit in a current mode logicbuffer mode based on a control signal by providing current from a firstcurrent source through a first switch circuit, a first resistor, and asecond switch circuit based on a first input signal provided to thefirst switch circuit during the current mode logic buffer mode and byproviding the current from the first current source through a thirdswitch circuit, a second resistor, and the second switch circuit basedon a second input signal provided to the third switch circuit during thecurrent mode logic buffer mode; and buffering the differential inputsignal received at the first and the second inputs to generate thedifferential output signal at the first and the second outputs in anH-bridge buffer mode based on the control signal.
 20. The method ofclaim 19 further comprising: coupling the second switch circuit to anode at a first voltage during the current mode logic buffer mode; andcoupling the second switch circuit to a node at a second voltage duringthe H-bridge buffer mode.